Refereed Journal Publications

Naif Tarafdar, Nariman Eskandari, Varun Sharma, Charles Lo and Paul Chow.Gala- pagos: A Full Stack Approach to FPGA Integration in the Cloud.
IEEE Micro, 2018
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Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie Enright Jerger and J. Gregory Steffan. DART: A Programmable Architecture for NoC Simulation on FPGAs.
IEEE Transactions on Computers, 2014
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Refereed Conference Publications

Charles Lo and Paul Chow. Hierarchical Modelling of Generators in Design-Space Exploration.
20th International Symposium on Field-Programmable Custom Computing Machines (FCCM’20), 2020 (acceptance rate: 21%)
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Charles Lo and Paul Chow. Multi-Fidelity Optimization for High-Level Synthesis Directives.
28th International Conference on Field Programmable Logic and Applications (FPL’18), 2018
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Charles Lo and Paul Chow. Model-Based Optimization of High Level Synthesis Directives.
26th International Conference on Field Programmable Logic and Applications (FPL’16), 2016 (acceptance rate: 21%)
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Charles Lo and Paul Chow. A High-Performance Architecture for Training Viola-Jones Object Detectors.
International Conference on Field-Programmable Technology (FPT’12), 2012 (acceptance rate: 21%)
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Zhongduo Lin, Charles Lo and Paul Chow. K-means Implementation on FPGA for High-Dimensional Data Using Triangle Inequality.
22nd International Conference on Field Programmable Logic and Applications (FPL’12), 2012 (acceptance rate: 28%)
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Charles Lo and Paul Chow. Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI.
19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’11), 2011 (acceptance rate: 26%)
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Patents

H. Styles, J. Fifield, R. Wittig, P. James-Roxby, S. Santan, D. Varma, F. Martinez Vallina, S. Zhou, C. Lo,
“Heterogeneous multiprocessor platform targeting programmable integrated circuits,” US Patent #9,846,660, Issued December 2017

H. Styles, J. Fifield, R. Wittig, P. James-Roxby, S. Santan, D. Varma, F. Martinez Vallina, S. Zhou, C. Lo,
“Heterogeneous multiprocessor program compilation targeting programmable integrated circuit,” US Patent #9,218,443, Issued December 2015

Presentations

Charles Lo and Paul Chow. Multi-Fidelity Optimization for High-Level Synthesis Directives.
At the 28th International Conference on Field Programmable Logic and Applications (FPL’18), Dublin, Ireland, 2018

Charles Lo and Paul Chow. Model-Based Optimization of High Level Synthesis Directives.
At the 26th International Conference on Field Programmable Logic and Applications (FPL’16), Lausanne, Switzerland, 2016

Charles Lo and Paul Chow. A High Performance Architecture for Training Viola-Jones Object Detectors.
At the International Conference on Field-Programmable Technology, Seoul, Korea, 2012

Charles Lo and Paul Chow. A High Performance Architecture for Training Viola-Jones Object Detectors.
At the Connections: University of Toronto Graduate Symposium, Toronto, Canada, 2012

Charles Lo and Paul Chow. Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI.
At the 19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’11), Monterey, USA, 2011

Charles Lo and Paul Chow. Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI.
At the University of Toronto FPGA Seminar, Toronto, Canada, 2011

Charles Lo and Paul Chow. Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI.
At the CMC Microsystems 2010 Annual Symposium TEXPO Demonstration, Ottawa, Canada, 2010